Automating IEEE 1500 Core Test—An EDA Perspective

THE CURRENT TREND of SoC design has made conventional test methodologies increasingly difficult. Performing brute-force test pattern generation (ATPG) on the entire SoC is often infeasible, because the design can exceed the test pattern generator’s capabilities. At other times, some black-box third-party cores within the SoC might have their own test patterns generated at the core boundary. IEEE Std 1500 has been developed primarily to address such complex scenarios encountered while testing SoC designs. IEEE 1500 describes how the cores within a SoC can be wrapped with IEEE-1500-compliant logic (called a wrapper) such that the overall task of testing the SoC is made much simpler. Researchers have published extensively on building IEEE-1500-compliant wrappers, and on their verification for compliancy. Additionally, research has been conducted on building test access mechanisms (TAMs) at the SoC level that efficiently harness cores, wrapped in accordance with IEEE 1500, that are embedded in the SoC. This article discusses CAD support for automated IEEE 1500 wrapper generation, verification, and test generation in a production environment. In particular, we show how to combine IEEE 1500 wrapper synthesis with test data compression to reduce the test data volume and test application time of wrapped cores. Test data compression is not a new concept, and has been described previously. One of the significant contributions of this article is to incorporate the test compression structures into the wrapper shell in a manner that retains IEEE 1500 compliance while also providing the benefits of compression. In this article, we also provide some solutions to the problem of migrating core test patterns to the SoC.